1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a process in which a nitrogen incorporated epitaxial layer is interposed between a gate dielectric and a semiconductor substrate to serve as a barrier layer therebetween.
2. Description of the Related Art
Fabrication of metal-oxide-semiconductor ("MOS") transistors is well-known. The manufacturing process begins by lightly doping a single crystalline silicon substrate with n-type or p-type species. Active areas of the substrate in which the transistors and other active devices will reside are then isolated from other active areas with isolation structures. Isolation structures may comprise shallow trenches in the substrate which are filled with a dielectric. Isolation structures may alternatively comprise local oxidation of silicon ("LOCOS") structures. A gate oxide (i.e., silicon dioxide) is then formed upon the substrate by thermally oxidizing the silicon-based substrate. A gate conductor is formed by depositing polycrystalline silicon ("polysilicon") upon the gate dielectric, followed by patterning the polysilicon using typical masking and etching techniques. Subsequently, the polysilicon gate conductor and source/drain regions arranged within the substrate on opposite sides of the gate conductor are concurrently doped with a high dosage of n-type or p-type dopants. If the impurity dopant is n-type, then the resulting transistor is referred to as an NMOS device. Conversely, if the impurity dopant is p-type, then the resulting transistor is referred to as a PMOS device. An integrated circuit which employs both NMOS and PMOS devices is generally known as a complementary MOS or CMOS circuit.
The resistivity of the polysilicon gate conductor is reduced by the introduction of impurities into the structure. Enough dopants are introduced so that the sheet resistance of the gate conductor is reduced to, in some instances, less than approximately 500 ohms/sq. In an ion implantation process, the depth at which the dopants are implanted can be controlled by adjusting the energy provided to the ions by the ion implantation equipment. However, the minimum depth of implantation is limited to between 200.ANG. and 400.ANG. because the energy of each ion is typically too large to permit a lesser depth of implantation.
Subsequent processing steps may require heating of the semiconductor topography. For example, a post-implant anneal is often performed to position and activate the dopants implanted into the source/drain regions and the gate conductor. Dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate than dopants with a low diffusivity. For instance, boron, which is commonly used to dope the polysilicon gate and the source/drain regions of an NMOS device, undergoes fast diffusion. On the other hand, arsenic, which is typically used to dope the polysilicon gate and the source/drain regions of a PMOS device, is a slow diffuser. Unfortunately, dopants, like boron, which readily migrate during heat treatment may diffuse from the gate conductor through the gate oxide and into the channel region of the transistor. Boron penetration into the channel can lead to undesirable effects, such as an increase in electron trapping, a decrease in low-field hole mobility, degradation of the transistor drive current, and increased subthreshold current.
In an attempt to prevent the diffusion of impurities into the channel region, barrier atoms are commonly incorporated into the gate oxide/channel interfacial region. For example, nitrogen is commonly introduced into the interfacial region by annealing the semiconductor topography in an ambient comprising N.sub.2. Available N atoms may react with Si atoms and O atoms of the gate oxide to form silicon oxynitride ("oxynitride"), terminating any dangling bonds within the gate oxide. The presence of strong N-O bonds of oxynitride throughout the gate oxide would serve to reduce the entrapment of hot carriers within the gate oxide. Further, single N atoms would block the migration pathways into and through the gate oxide, inhibiting fast diffusing impurities from passing from the gate conductor into the channel region.
Unfortunately, only a small fraction (e.g., 1/1000) of the N.sub.2 molecules actually break up into separate N atoms upon entering the gate oxide. It is believed that the N.sub.2 molecules, unlike individual N atoms, may be too large to fill interstitial positions and vacancies within the gate oxide. Consequently little if any protection against impurity diffusion through the gate oxide is accomplished by the N.sub.2 diffusion process.
Ion implantation of barrier atoms, e.g., N atoms, into the gate oxide/channel interfacial region has also been employed as a barrier to hot carriers or to prevent species from passing into and out of the gate oxide. The gate oxide may be less than 50.ANG. thick to ensure high capacitive coupling between the channel and the gate conductor. Ion implantation involves accelerating the ions in an electric field to increase the energy of each ion to greater than 10 keV. Absent the ability to achieve lower energies for the ions, the ions are implanted into a medium to a minimum depth of between 200 and 400.ANG.. Accordingly, atoms implanted into the gate oxide are situated and thereafter tend to migrate well-below the gate oxide/channel interface. The atoms thusly placed fill no interstitial and vacancy positions within the critical gate oxide. Therefore, the atoms provide little, if any, barrier against the migration of impurities from the gate conductor into the channel and to the injection of hot carriers into the gate oxide.
It would therefore be of benefit to develop a more effective method for forming a diffusion barrier between the gate conductor and the channel region of a transistor to prevent the migration of dopants into the channel region and/or hot carriers into the gate dielectric. Ion implantation of barrier atoms using conventional methods should be avoided to ensure that the diffusion barrier is accurately positioned in the gate dielectric/channel interfacial region. Otherwise, the barrier atoms might be implanted beneath the interfacial region where they would provide little protection against dopant diffusion into the channel. It is also desirable that the concentration of nitrogen atoms be maximized to enhance the barrier properties of the diffusion barrier.